1. Field of the Invention
This invention relates generally to polysilicon fuse devices and more particularly, it relates to a polysilicon fuse structure of a new and novel construction for implementation within integrated circuit devices so as to permit programming.
2. Description of the Prior Art
In an article entitled "Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi.sub.2 and CoSi.sub.2 " and authored by Jerome B. Lasky et al., IEEE Transactions on Electron Devices, Vol. 38, No. 2, February 1991, pp. 262-269, there is reported the investigation of the phase transformation and stability of titanium silicide on n.sup.+ diffusions. Similar studies were performed for cobalt silicide on n.sup.+ and p.sup.+ diffusions.
Further, a study was performed on a new programmable element based on agglomeration of the titanium-silicide layer on top of poly fuses. This is described and illustrated in an article entitled "A PROM Element Based on Salicide Agglomeration of Poly Fuse in a CMOS Logic Process" and authored by Mohsen Alavi et al., 1997 IEEE, 1997 IEDM Technical Digest, 1997, pp. 855-858. In FIGS. 6(a)-6(d) at page 857 there are shown various fuse shapes each having a length of about 2 .mu.m and a width in the range of 0.22 .mu.m to 0.27 .mu.m.
As is generally well-known, in computer systems and other related electrical equipment there are used a large number of different types of semiconductor IC memory devices, such as programmable read-only memory (PROM) programmable logic arrays (PLA), and redundancy memory arrays. Fuse arrays are typically formed during the manufacturing of these semiconductor IC memory devices. The purpose of the fuses in the PROM or PLA devices is to customize it for a specific application. In particular, the PROM or PLA device is programmed by opening or blowing the appropriate fuses in selected memory cells. In connection with the redundancy memory arrays, the fuses are used to replace defective memory cells with spare substitute cells which were fabricated in the array during the manufacturing process.
There have been provided heretofore in the prior art various types of fuse devices. The most common type fuse is a metal link formed of tungsten. In order to blow the fuse, current is driven through the metal link so as to heat up the same to its melting point and to thus cause a break in the link to occur. However, the metal link fuses are not viable for use with the IC memory devices formed using the newer process technologies having thinner gate oxides since they require large programming currents of over 100 milliamperes to blow. In addition, the metal link fuses may be caused to be inappropriately reconnected by an electromigration phenomenon which occurs during operations.
As a result, there has now been developed a polysilicon fuse which requires a lesser amount of current than the metal link fuse to open the same during programming. For a similar geometry, the current required to blow by fracturing (e.g., vaporization of the poly material) the polysilicon fuse is on the order of 50-100 milliamperes. This is referred to as a "hot blow." The polysilicon fuse may have in some cases a multi-layer construction consisting of a polysilicon layer and a silicide layer disposed on top of the polysilicon layer. This latter type of polysilicon fuse is referred to as a "silicided polysilicon fuse." The silicided polysilicon fuse is blown by a phase transformation (e.g., agglomeration at the current of 10-20 milliamperes) of the silicide layer. This is referred to as a "soft blow."
In FIG. 1(a), there is shown a top plan view of a conventional silicided polysilicon fuse device 10 which is quite similar to the one illustrated in FIG. 6(a) of the Alavi et al. article and is labeled as "Prior Art." The fuse device 10 is comprised of a first contact region 12, a second contact region 14 separated from the first contact region 12, and a fuse region 16 defined by a single narrow strip formed between the first and second contact regions. In FIG. 1(b), there is shown a cross-sectional view of the fuse device 10 taken along the line 1--1 of FIG. 1(a). As can be seen, the fuse device 10 includes a polysilicon layer 18 and a silicide layer 20 formed on the top surface of the polysilicon layer 18. The polysilicon layer 18 has a thickness of approximately 0.25 .mu.m and a sheet resistance of about 1,000 ohms/sq. in. The silicide layer 20 may be made of a titanium silicide (TiSi.sub.2) film or other like silicides. The silicide layer 20 has a thickness of approximately 0.025 .mu.m and a sheet resistance of about 10 ohms/sq. in.
In operation, the fuse device 10 has a first resistance prior to being programmed or "blown" and has a much higher second resistance after programming or blowing. Prior to the blowing of the fuse device 10, the first resistance is determined by the resistance of the silicide layer 20. After the fuse device 10 is blown, a discontinuity will be formed in the silicide layer 20. This second resistance of the fuse device will be increased to a higher value and is dependent upon the ratio of the resistance of the polysilicon layer to the resistance of the silicide layer 20. As a programming voltage is applied across the first and second contact regions 12, 14 (FIG. 1(a)), current will flow from the first contact region 12, through the narrow strip 16, to the second contact region 14. The current flowing therethrough will cause the silicide layer 20 to heat up and the silicide itself will agglomerate to create a discontinuity. Since the silicide layer 20 has a lower resistance than the polysilicon layer 18, there will be caused an increased resistance to occur.
Nevertheless, the non-silicided polysilicon fuses or silicided polysilicon fuses of the existing designs suffer from the disadvantages that they both use a single narrow strip defining the fuse element which is blown by fracturing the polysilicon layer or phase transformation of the silicide layer so as to increase the resistance. As can thus be seen, the fuse device 10 of FIG. 1 has either an unprogrammed state where the fuse is not blown (unburned) or a programmed state where it is blown (burned). Since the unblown or unburned (unprogrammed) fuse has a lower resistance, this may be interpreted as a low or "0" logic level. On the other hand, the blown or burned (programmed) fuse has a higher resistance, this may be interpreted as a high or "1" logic level.
However, there are times where it would be desirable to selectively program the amount of current within a predetermined range that is passed through the integrated circuit device during its normal operating conditions. This is accomplished by the inventors of the present invention by the provision of a new polysilicon fuse structure having multiple fuse regions each with a different width and/or length dimension. As a result, dependent upon the amount of programming current applied, a selectable number of the multiple fuse regions will be secuentially blown so as to provide the proper resistance thereby limiting the amount of current that is passed to the integrated circuit device. This type of programming is referred to as analog programming where one of a number of different resistance values within a range can be selected.